This invention can relate to integrated circuit (IC) devices. More particularly, this invention can relate to staggered logic array blocks (LABs) on IC devices.
IC devices are well-known in the art, and can include a plurality of general-purpose programmable logic elements that can be programmed to perform a wide variety of tasks. Using such programmable logic elements allows manufacturers of electronic circuitry to avoid the need to separately design and build individual logic circuits on each IC device. IC devices that use programmable logic elements can include, for example, programmable logic devices (PLDs) and structured application-specific integrated circuits (ASICs). For simplicity, the discussion herein focuses chiefly on PLDs, but it will be understood that the principles of the present invention can also be applied to other types of IC devices.
The basic building block of a PLD is a logic element (LE) that is capable of performing limited logic functions on a number of input variables. Each LE in a PLD typically provides a combinational logic function such as a look-up table (LUT), and one or more flip-flops. To facilitate implementation of complex logic functions, LEs in a PLD are often arranged in groups, to form one or more LABs. For example, each LAB in a PLD may include eight LEs, and the LAB may be programmed to provide any one of a plurality of logic functions by using control bits. The LABs in a PLD, meanwhile, are often arranged in a one-dimensional or two-dimensional array, and are programmably connectable to each other using a PLD routing architecture.
The routing architecture of a PLD typically includes an array of signal conductors having programmable interconnections that are used to route data and output enable signals. For example, the routing architecture can include several horizontal and vertical conductor channels, where each of these channels can include, respectively, one or more horizontal or vertical signal conductors. In addition, the conductors in a given channel can span all of the LABs in a given row or column or, alternatively, can span only a subset of the LABs in the row or column (e.g., 4 LABs). These types of conductors are generally referred to herein as “segmented conductors,” and channels containing segmented conductors are referred to herein as “segmented channels.”
The horizontal and vertical channels of a PLD can allow the LABs of the PLD to communicate with each other. Communications between a given pair of LABs can require the use of only a single conductor channel (e.g., LABs in the same row or column can communicate using a single horizontal or vertical channel, respectively) or can require the use of multiple conductor channels (e.g., LABs that are laid out diagonally from each other might communicate using a horizontal channel in combination with a vertical channel). In addition, certain routing architectures can allow adjacent LABs to communicate with each other without the use of any conductor channel (e.g., because an output of one LAB can be selectably coupled to an input of an adjacent LAB). In general, the latency of communicating with another LAB using a single conductor channel (or without using any routing channels) tends to be lower than the latency of communicating with another LAB using multiple routing channels.
In view of the foregoing, it would be desirable to provide an architecture that allows each LAB to communicate with a greater number of other LABs using only a single conductor channel. Additionally, it would be desirable to provide an architecture that allows each LAB to communicate with a greater number of other LABs without using any conductor channel.